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VHDL05
- ALU算术逻辑运算模块设计代码。内容简单。是个不错的代码，学习的人可以下载参阅。-ALU arithmetic logic operations module design code. Simple. Is not a bad code, people can download the study refer to.
project
- 利用VHDL实现三个简单的程序：BCD加法器；ALU算术逻辑单元；简单密码锁设计，具有输入密码和数据比较两种功能，由M决定是写入还是开锁。而数据写入是采用列地址与输入数相结合的的方法，存入初始密码；开锁时，密码以输入，再输入的数据逐个与输入的一组数据比较，完全吻合则开锁。-The use of VHDL to accomplish three simple procedures: BCD adder ALU arithmetic logic unit simple lock design,
VHDLmipsPipeline
- 32 位MIP流水线CPU设计，5 stage，代码详细，包括ALU,存储器,寄存器等，是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
32Bitaludesign
- Design of simple 32 bit alu for SPARTAN 3 paltform
CPUcoa-course-design
- 简单的cpu设计，包括memory，alu运算器，comp比较器以及控制器control，寄存器register等的vhdl编写的程序。-A simple cpu design, including memory, alu arithmetic logic unit, comp comparator and controller control, such as vhdl register register write programs.
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
DiSyLab1
- A vhdl design of a simple arithmetic and logic unit (alu)
ALUvhdlcoding
- it is the simple ALU VHDL program. it is used to design the high level computer system.
alu_simulation
- VHDL alu unit design and simulation with RAM, ROM, clock generator and 2 simple programs to execute.
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
SSALU
- VHDL设计8位算术逻辑单元（alu），实现清零、逻辑乘、逻辑加、逻辑异或、算术加、逻辑左移一位、逻辑右移一位等功能-VHDL design eight the arithmetic/logic unit (alu), realize the reset, logic, logic and, by different or, arithmetic and logic, logical moves left a, logic move to the right a etc.
ALU
- VHDL设计的ALU，可以添加到CPU的编写者-VHDL lanuage design for ALU
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
Alu-with-seven-segmetn-output
- This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be eas
ALU16bit
- design ALU 16 bit in VHDL
alu64
- design and impliment alu 64 bit in vhdl
alu1
- 本文是基于vhdl的8位cpu ip core设计alu-This article is based on the 8 vhdl cpu ip core design alu